Bump formed on semiconductor device chip and method for manufacturing the bump

ABSTRACT

A bump of a semiconductor chip comprises a plurality of bond pads formed on a semiconductor chip, a conductive bump formed on the bond pads; and a sidewall insulating layer formed on sidewalls of the conductive bump. It is possible for the semiconductor chip to prevent electrical shorts and improve productivity even though a pitch of bond pad is decreased.

[0001] This application claims priority from Korean Patent ApplicationNo. 2002-0027440, filed on May 17, 2002, the contents of which areincorporated herein by this reference in their entirety.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor device, and moreparticularly, to a bump of a semiconductor chip, a method formanufacturing the bump, and a package using the bump.

[0004] 2. Description of the Related Art

[0005] As semiconductor devices become more highly integrated, thenumber of pads formed on the surface of a semiconductor chip increase,while the pitch between the metal pads becomes narrow. This causesvarious problems when the semiconductor chip is mounted on a printedcircuit board (PCB).

[0006] In particular, when packaging a semiconductor chip using achip-on-glass (COG) method, it is very difficult to reduce the pitchbetween the metal pads because of possible electrical shortstherebetween, as the pitch between bumps formed on the metal pad becomesnarrower.

[0007]FIG. 11 is a cross-sectional view showing a conventional bump of asemiconductor chip, and FIG. 12 is a cross-sectional view of asemiconductor device mounted on a PCB with the COG method. Referring toFIGS. 11 and 12, the conventional semiconductor chip bump comprises bumpmetal layers 1220 and 1230 formed of a metal compound on a metal pad1180 which is formed on a semiconductor chip 1100 in order to protrudeupward with a predetermined height. Here, the reference number 1190denotes a passivation film, which acts as a protective layer.

[0008] When the conventional semiconductor chip 1100 is mounted on a PCB1400 through the COG method, as shown in FIG. 12, adjacent bump metallayers 1220 and 1230 become very close to each other within a criticaldistance. Consequently, the anisotropic conductive layer 1350 loses itsrole as an insulating layer and is likely to be shorted. Therefore,there are limits to which the pitch between the metal pads 1180 formedon the semiconductor device can be reduced, in designing the bumppitches using the COG method. Accordingly, the conventional bumpstructure has become more and more unsuitable for use inhighly-integrated semiconductor chips.

SUMMARY OF THE INVENTION

[0009] To solve the above-described problems, it is an object of thepresent invention to provide a semiconductor chip bump that does notcause electrical shorts when it is mounted on a PCB or a packagesubstrate, even when the interval between the bond pads formed on thesemiconductor chip becomes narrow, and a method for manufacturing thesame.

[0010] According to one embodiment, a bump of a semiconductor chipcomprises a plurality of bond pads formed on a semiconductor chip, aconductive bump or a metal bump formed on the bond pads; and a sidewallinsulating layer formed on sidewalls of the conductive bump.

[0011] According to another embodiment, an insulating layer is formed ona semiconductor chip on which a plurality of bond pads are formed. Acontact hole is formed in the insulating layer to expose the bond pads.Thereafter, a bump is formed in the contact hole, and a sidewallinsulating layer is formed on the sidewalls of the bump.

[0012] The insulating layer is preferably formed of a polymer material.A polymer material such as a polymide precursor is coated on the surfaceof a semiconductor substrate with, for example, a spin coating methodand is thermally processed for a predetermined time so that a solidpolymer layer is formed.

[0013] According to one embodiment, the contact hole is formed in thepolymer layer using laser to expose the bond pads. Alternatively, thecontact hole can also be formed by dry etching using plasma.

[0014] According to one aspect of the present invention, forming a metalbump includes forming a seed metal on the exposed metal pad using, forexample, non-electrolytic plating, forming on the seed metal a metalpacking layer of nickel or nickel alloy, and filling the inside of thecontact hole to a predetermined height. The capping metal layer isformed on the metal packing layer. The capping metal layer is preferablyformed of gold (Au).

[0015] The method of forming the sidewall insulating layer on thesidewall of the metal pump includes etching the polymer layer to adesired amount by, for example, irradiating laser while leaving aportion of the polymer layer on the sidewalls of the bump.

[0016] As described above, the bump of a semiconductor chip of thepresent invention and a method for manufacturing the same can preventshorts, even when the interval between the bond pads becomes narrow asthe line width of the semiconductor chip becomes narrow because thesidewall of the bump is surrounded by an insulating layer andelectrically insulated.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above object and advantages of the present invention willbecome more apparent by describing in detail preferred embodimentsthereof with reference to the attached drawings in which:

[0018]FIG. 1 is a cross-sectional view of a bump formed on asemiconductor chip of the present invention;

[0019]FIG. 2 is a cross-sectional view of another embodiment of the bumpformed on a semiconductor chip of the present invention;

[0020]FIGS. 3 through 6 are cross-sectional views showing a sequence ofsteps in a method for manufacturing the bump formed on a semiconductorchip of the present invention;

[0021]FIGS. 7 and 8 are cross-sectional views showing another embodimentof the method for manufacturing the bump formed on a semiconductor chipof the present invention;

[0022]FIG. 9 is a cross-sectional view showing a COG package of asemiconductor chip of the present invention;

[0023]FIG. 10 is a schematic plane view showing an array of bond padsformed on the semiconductor chip;

[0024]FIG. 11 is a cross-sectional view showing a bump of a conventionalsemiconductor chip; and

[0025]FIG. 12 is a cross-sectional view showing a COG package of aconventional semiconductor chip.

DETAILED DESCRIPTION OF THE INVENTION

[0026] The present invention will now be described more fully withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. The invention may, however, be embodied inmany different forms and should not be construed as being limited to theembodiments set forth herein; rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the concept of the invention to those skilled in the art.

[0027]FIG. 1 is a cross-sectional view showing a bump 200 formed on asemiconductor chip 100 according to an embodiment of the presentinvention. Referring to FIG. 1, the bump 200 formed on the semiconductorchip 100 comprises a plurality of bond pads 180 formed on the surface ofthe semiconductor chip 100, bump metal layers 220 and 230 overlying andelectrically connected to the bond pads 180. The bump 200 includes asidewall insulating layer 210′ surrounding the sidewalls of the bumpmetal layers 220 and 230. Here, reference number 190 denotes apassivation layer formed on the semiconductor chip as a protectionlayer.

[0028] It is not shown, but the metal pad 180 is formed along aperiphery of the semiconductor chip 100 at a predetermined interval sothat individual memory or the LOGIC devices formed in the semiconductorchip 100 can be electrically connected to an external device such asPCB. The predetermined interval corresponds to the connecting pads (notshown) formed on the PCB on which the semiconductor chip 100 is mounted.

[0029] The bump 200 preferably comprise a packing metal layer 22contacting the metal pad 180, and a capping metal layer 230 stacked onthe packing metal layer 220. The packing metal layer 220 preferablycomprises a metal material having good contact resistance and bondingproperties with the metal pad 180, for example, Nickel Ni or Nickelalloy. Also, the capping metal layer 230 is preferably formed of gold.One skilled in the art will appreciate that other suitable conductivematerials to form the packing metal layer 220 or the capping metal layer230 can be used within the spirit and scope of the present invention.

[0030] The sidewall insulating layer 210′ is formed on sidewalls of thebump metal layers 220 and 230, and formed of an insulating film such aspolyamide or epoxy which is a type of polymer resin. The sidewallinsulating layer 210 can prevent electrical shorts between the bumps 200during a back-end packaging process like resin filling. Also, damage tothe bump metal layers 220 and 230 can be prevented by minimizing an areaof the bump metal layers 220 and 230 exposed to the outside.

[0031] As shown in FIG. 9, when the semiconductor chip 100 is mounted ona PCB 400 by a COG method, an anisotropic conductive film 350 can beused to connect the semiconductor chip 100 to connection pads 480 formedon the PCB 400. The anisotropic conductive film 350 has both conductivecharacteristics, because of conductive particles formed therein, andinsulation characteristics, when the conductive particles are separatedfrom each other more than a predetermined distance. However, if thedistance between the adjacent bump metal layers 220 and 230 becomes toonarrow, i.e., narrower than a critical distance between the adjacentbump metal layers 220 and 230, the sidewall insulating layer 210 formedon the sidewalls of the bump metal layers 220 and 230 acts as aninsulator and prevents short circuits therebetween.

[0032]FIG. 2 is a cross-sectional view showing a bump of a semiconductorchip according to another embodiment of the present invention. Referringto FIG. 2, a bump 200 includes a packing metal layer 220 formed within asidewall insulating layer 210′ and slightly exceeds the upper portion ofthe sidewall insulating layer 210′. A capping metal layer 230 is formedto cover the top of the packing metal layer 220. The bump metal layers220 and 230 having the above configuration are formed to protrude ontothe sidewall insulating layer 210′ to have a width greater than thecapping metal layer 230 of FIG. 1. Thus, the bump 200 can easily contactthe outer coupling pad (not shown) and have a low contact resistance dueto a broad contact area therebetween.

[0033]FIGS. 3 through 6 are cross-sectional views sequentially showing amethod of manufacturing a bump formed on a semiconductor chip accordingto an embodiment of the present invention.

[0034] Referring to FIG. 3, a polymer material is coated on asemiconductor chip 100, including a passivation layer 190, on which asemiconductor device is fabricated through a predetermined manufacturingprocess. The semiconductor chip 100 may then be thermally treated by amethod such as baking in a baking oven at a predetermined temperature.Consequently, a polymer layer 210 is disposed over the semiconductorsubstrate 100 to form a sidewall insulating layer 210′. See FIG. 6. Thepolymer material layer 210 may be, but not limited to, polymide orepoxy.

[0035] Referring to FIG. 4, a contact hole 200 a is formed in thepolymer layer 210 to expose the surface of the metal pad 180 through apredetermined patterning process. The contact hole 200 a may be formed,for example, by irradiating a laser on a portion where the metal padneeds to be exposed. In addition, in the case of a photoresist polymer,a contact pattern for exposing the metal pad 180 is formed by coating aphotoresist on the surface of the semiconductor chip 100 andaligning/exposing the same. The contact hole 200 a for exposing themetal pad 180 is formed by etching the passivation layer 190 by dryetching using the patterned photoresist as a mask.

[0036] Referring to FIG. 5, a seed metal (not shown) is formed on thesurface of the exposed metal pad 180 inside the contact hole 200 a, anda packing metal layer 220 is formed preferably using non-electrolyticplating. It is preferred that the packing metal layer 220 be formed ofnickel or nickel ally because it has low contact resistance and goodadhesion properties with aluminum that forms the metal pad 180. Next, acapping metal layer 230, preferably formed of gold (Au), is formed onthe packing metal layer 220. The packing metal layer 220 is preferablyformed shallower than the depth of the contact hole 200 a. Even thoughthe capping metal layer 230 is formed on the packing metal layer 220, itis possible to leave a recessed area in the center of contact hole 200 abecause the contact hole 200 a is lower than the neighboring sidewallinsulating layer 210. Accordingly, it is convenient to attach anexternal connection terminal such as a solder ball on the bump 200.

[0037] Referring to FIG. 6, a photoresist is coated and patterned on thesurface of a semiconductor chip 100 to form a sidewall insulating layerpattern 300. The portions of the polymer layer 210 can be removed by,for example, laser irradiation. Consequently, the sidewall insulatinglayer 210′ is formed to remain on the sidewalls of the bump metal layers220 and 230 and the other portions of the polymer layer 210 can beremoved.

[0038] With the method described above, the polymer layer 210 is etchedto leave a portion of the polymer layer 210 on the passivation layer 190to a predetermined thickness, for example, 2-5 microns to serve as aprotection layer. Alternatively, the polymer layer 210 is removed toexpose the passivation film 190. Thus, the laser irradiation method hasan advantage in that the thickness of the polymer layer 210 can beprecisely controlled through pulses.

[0039]FIGS. 7 and 8 are cross-sectional views showing another embodimentof the method for manufacturing a bump of a semiconductor chip of thepresent invention.

[0040] Referring to FIG. 7, after a contact hole 200 a is formed in apolymer layer 210, a seed metal is formed within the contact hole 200 aon a metal pad 180. Then, a packing metal layer 220 is formed in thecontact hole 200 a using non-electrolytic plating in the same manner asdescribed with respect to FIG. 5. The packing metal layer 220 is grownhaving a flange shape on side walls of the sidewall insulating layer 220in the contact hole 200 a. The packing conductive layer 220 is overgrownto the outside of the contact hole 200 a. Next, a capping metal layer230, preferably formed of gold (Au), is formed on the packing conductivelayer 220. A sidewall insulating layer 210 is etched using the cappingmetal layer as a mask through, for example, dry etching.

[0041] The method for manufacturing a bump having the above describedconfiguration has an advantage of reducing manufacturing costs byomitting a photo process.

[0042] Thus, the present invention provides a semiconductor chip bumpthat can reduce electrical shorts between bump metal layers especiallyin a highly integrated circuit.

[0043]FIG. 9 is a cross-sectional view of a COG package in which a bumpof a semiconductor chip is attached to a PCB by a COG method. Referringto FIG. 9, the COG package according to an embodiment of the presentinvention comprises a PCB 400 on which a plurality of connection pads480 are formed; a semiconductor chip including a plurality of bond pads180 formed to face the PCB 400 and correspond to the connection pads480, bump metal layers 220 and 230 overlying the metal pad 180, and aninsulating layer 210′ formed on the sidewalls of the bump metal layers;and an anisotropic conductive film 350 interposed between the PCB 400and the semiconductor chip 100 and electrically connecting theconnection pads 480 and the bump metal layers 220 and 230.

[0044] The insulating layer 210′ is preferably formed of a polymer suchas polymide or epoxy, using a spin coating method. The anisotropicconductive film 350 including conductive particles is conductive at theportion where the connection pad 480 and the bump metal layer 230contact, and acts as an insulating layer at other portions.

[0045] According to embodiments of the present invention, electricalshorts do not occur in the COG package because the sidewall of the bumpmetal layer A is surrounded by the insulating layer 210′ andelectrically insulated, even though the distance from other bump metallayers B becomes narrower, or even when the pitch between bond padsbecomes narrow.

[0046] In addition, the method for manufacturing a semiconductor chip ofthe present invention can reduce production costs by omitting a photoprocess. Furthermore, the method for manufacturing a semiconductor chipof the present invention can reduce soldering fails by forming a solderball on the bump metal layer in a stable manner.

[0047] While this invention has been particularly shown and describedwith reference to preferred embodiments thereof, it will be understoodby those skilled in the art that various changes in form and details maybe made therein without departing from the spirit and scope of theinvention as defined by the appended claims.

What is claimed is:
 1. A bump of a semiconductor chip, comprising: aplurality of bond pads formed on a semiconductor chip; a conductive bumpformed on the bond pads; and a sidewall insulating layer formed onsidewalls of the conductive bump.
 2. The bump of a semiconductor chip ofclaim 1, wherein the sidewall insulating layer is formed of a polymermaterial such as polymide or epoxy.
 3. The bump of a semiconductor chipof claim 1, wherein the conductive bump comprises: a conductive packinglayer that contacts the conductive pad; and a capping conductive layerformed on the conductive packing layer.
 4. The bump of a semiconductorchip of claim 3, wherein the conductive packing layer is formed ofnickel alloy.
 5. The bump of a semiconductor chip of claim 4, whereinthe conductive packing layer is formed by non-electrolytic plating. 6.The bump of a semiconductor chip of claim 3, wherein the cappingconductive layer is formed of gold (Au).
 7. The bump of a semiconductorchip of claim 1, wherein the conductive packing layer extends above atop surface of the sidewall insulating layer.
 8. A method formanufacturing a semiconductor chip, the method comprising; forming aninsulating layer on a semiconductor chip having a plurality of bond padsformed thereon; forming a contact hole in the insulating layer to exposethe bond pads; forming a bump conductive layer in the contact hole; andforming a sidewall insulating layer on sidewalls of the bump conductivelayer by removing a portion of the insulating layer.
 9. The method ofclaim 8, wherein the insulating layer comprises a polymer material. 10.The method of claim 9, wherein the polymer material is one of polymideor epoxy.
 11. The method of claim 8, wherein the forming a contact holein the insulating layer comprises etching a portion of the insulatinglayer using laser irradiation.
 12. The method of claim 8, wherein theforming a bump conductive layer in the contact hole comprises; forming aseed metal on the exposed bond pads; forming a metal packing layer onthe seed metal; and forming a capping metal layer on the metal packinglayer.
 13. The method of claim 12, wherein the metal packing layer isformed of nickel Ni or nickel alloy.
 14. The method of claim 12, whereinthe capping metal layer is formed of gold (Au).
 15. The method of claim12, further comprising forming a solder ball on the capping metal layer.16. The method of claim 8, wherein the forming a sidewall insulatinglayer on sidewalls of the bump conductive layer comprises: forming aphotoresist pattern overlying the bump conductive layer; and etching theinsulating layer to leave a portion of the insulating layer on thesidewalls of the bump conductive layer to form the sidewall insulatinglayer, using the photoresist pattern as a mask.
 17. The method of claim16, wherein the etching comprises laser irradiation.
 18. The method ofclaim 8, wherein the forming a sidewall insulating layer on sidewalls ofthe bump conductive layer by removing a portion of the insulating layercomprises: over growing the bump conductive layer on a top of theinsulating layer to a predetermined height; and etching the insulatinglayer using the overgrown bump conductive layer as a mask.
 19. Themethod of claim 18, wherein the overgrowing the bump conductive layercomprises: forming a seed metal in the contact hole; growing a metalpacking layer on the seed metal and growing the metal packing layer toextend above the contact hole to a predetermined amount; and forming acapping metal layer on the metal packing layer.
 20. The method of claim18, wherein the metal packing layer is formed of nickel or nickel alloy.21. The method of claim 18, wherein the etching comprises laserirradiation.
 22. A chip-on-glass (COG) package comprising; a packagesubstrate having a plurality of connection pads; a semiconductor chipcomprising a plurality of bond pads arranged to face the plurality ofconnection pads and to be electrically connected thereto; a bump havingan insulating layer formed on sidewalls thereof, the bump overlying thebond pads; and an anisotropic conductive film interposed between thesemiconductor chip and the package substrate to electrically connect theconnection pads and the bump.
 23. The COG package of claim 22, whereinthe bump comprises: a packing metal layer formed on the bond pads; and acapping metal layer formed on the metal packing layer.
 24. The COGpackage of claim 23, wherein the packing metal layer is formed of nickelor nickel alloy, and the capping metal layer is formed of gold (Au). 25.The COG package of claim 22, wherein the insulating layer comprises apolymer.
 26. The COG package of claim 25, wherein the polymer layer isformed of one of polymide or epoxy.
 27. The COG package of claim 23,wherein the packing metal layer is formed by non-electrolytic plating.